Dynamic Power-Saving Adaptive Decision Feedback Equalizer Design for High-Speed Communication Systems
碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === In this thesis, we design a high-speed Adaptive Decision Feedback Equalizer (ADFE) with dynamic power saving mechanism. Our target is to provide ADFE architectures for high-speed communication systems. We propose two high-speed ADFE archite...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65828061187282662550 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === In this thesis, we design a high-speed Adaptive Decision Feedback Equalizer (ADFE) with dynamic power saving mechanism. Our target is to provide ADFE architectures for high-speed communication systems.
We propose two high-speed ADFE architectures named Type-I and Type-II Partial Unrolled Pipelined ADFE (PUP-ADFE) respectively in Chapter 4 . Furthermore, we also propose a dynamic power saving strategy for ADFE design in Chapter 5 .
All the ideas are verified from algorithm to physical implementation. Finally, we list our implementation results to show the achievements of our design.
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