Simultaneous Floorplanning and Power/Ground Network Synthesis

• Main Author: 楊士賢
• Other Authors: 張耀文
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/57432269908596784837

碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === Signal integrity is emerging as an important issue as very large scale integration (VLSI) technology advances to nanoscale regime. In today's deep submicron (DSM) technology, metal width tends to decrease with length increasing due to the complex system integration. Large current due to a large number of cells switching may cause unacceptable current-resistance (IR) drop. Faster switching frequencies and thinner wires with a lower supply voltage will increase the possibility of functional failures due to the excessive IR drops. Traditionally power distribution network analysis is performed during the transistor-level and post-layout verification. Iteration cost is high at the end of the design flow. In this thesis, in order to achieve the single-pass design methodology, we incorporate a power analysis algorithm into floorplanning stage for early power planning. To ensure the IR drop acceptable at post floorplan. Experimental results based on five MCNC benchmark circuits and a 0.25-um technology show that the predicted IR drop is reduced during the floorplanning stage. With the power analysis considered at the floorplanning stage, we can reduce the IR drop error at the post-layout verification stage.