Design of CMOS DLL and Data Recovery Circuit
碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === For the continuing scaling of CMOS process technologies, the speed performance of the VLSI system is increasing rapidly. As the frequency is rising, the problem of timing jitter for digital circuits model is more serious. It will decrease the speed and the respo...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/04557764507289666270 |