OFDM Baseband Transceiver Architecture Design and Implementation for IEEE 802.11a

• Main Authors: Wei-Hsiang Tseng, 曾維祥
• Other Authors: Chorng-Kuang Wang
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/49857649118069324996

碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === Due to the convenience of the wireless communication, the research of wireless local area network is expanding rapidly. In this thesis, the architecture of a baseband transceiver compliant with the physical layer specifications of IEEE 802.11a for wireless LAN is designed and implemented. The maximal supported data rate can achieve 54 Mbps. The transmitter can send the regulated packet format and comply with the transmit spectrum mask requirement of the standard. In the design of the receiver, an interpolator combing the removal of the cyclic prefix with a sliding window is proposed for all-digital timing recovery in multi-tone modulation transmissions. Following, with the aid of the delay correlator and match filter, the carrier recovery and symbol boundary detection are realized. By MMSE and LMS algorithms, the frequency-domain equalizer can deliver a sufficient SNR of the equalized symbol. Finally, the Radix-2/4/8 Single-path Delay Feedback architecture is exploited as the implementation of IFFT/FFT module which can be shared by the transmitter and the receiver for performing modulation and demodulation, respectively. For a specified SNR, the PER less than 10% can be achieved. This baseband transceiver is implemented in single chip by TSMC 0.25μm CMOS technology. This chip occupies about 3.5 mm x 3.5 mm chip area and consumes 109 mW at 2.5 V power supply.