10 GBASE Ethernet Receiver Front End Design
碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === 10Gb/s Ethernet is the next generation media interface for local area networks. Recently, 10Gb/s Ethernet realized in CMOS technology is under progress and aims for low power and low cost. The RF front-end consists of a low noise transimpedance amplif...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22583777155767088705 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === 10Gb/s Ethernet is the next generation media interface for local area networks. Recently, 10Gb/s Ethernet realized in CMOS technology is under progress and aims for low power and low cost. The RF front-end consists of a low noise transimpedance amplifier, and a limiting amplifier or AGC. The circuits must cover wide dynamic range and enough bandwidth to meet the bit error rate and jitter requirements. This thesis presents three front-end chips for different types of 10GBASE Ethernet and all are implemented in 0.18μm 1p6M CMOS technology. The first chip realizes a limiting amplifier with proposed AM to PM reducing cells operating at 3.125 Gb/s. This chip occupies a 1mm x 1mm chip area (0.14mm x 0.5mm active) and consumes 28 mW under a 1.8 V supply voltage. The second chip realizes a proposed 3.125 Gb/s exponential variable gain amplifier with temperature insensitive bias current and covers a 35 dB gain control range. This chip occupies a 0.5mm x 0.8 mm chip area (0.2mm x 0.5mm active) and consumes 67 mW. The final one integrates a transimpedance amplifier and a limiting amplifier operating at 10 Gb/s and the inductor is used in this design. The chip occupies a 1.1mm x 2.2mm chip area and consumes 63 mW under a 1.8V power supply. All the chips are verified from the post- layout simulation and some present experimental results.
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