| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === JPEG2000 is the next-generation still image compression standard. It outperforms the traditional JPEG on its excellent compression efficiency and numerous novel features. One of the superior features in JPEG2000 is the ability of accurate rate-distortion optimized rate control. However, the algorithm is complicated and not suitable for the hardware implementation.
An efficient JPEG2000 encoder design with novel rate-distortion optimizing techniques is proposed in this thesis. The feature of this design is the accurate optimized rate control ability that is suitable for the hardware implementation. None of the other existing designs have been able to handle the optimized rate control of JPEG2000 on the dedicated hardware yet. Furthermore, by the proposed feedback procedure of the rate control, the computation of the entropy coder EBCOT Tier-1, which contains most of the computational load in JPEG2000, can be greatly reduced almost without any PSNR degradation compared with the optimized results of the reference software. For general compression ratio, ex. 12, the computation cycles for Tier-1 can be reduced to 50%. For higher compression ratio, ex. 50, the computation can be further reduced to 20%.
The prototyping chip of the proposed rate control technique has been implemented in CMOS 0.25mm technology. Moreover, the integration of EBCOT Tier-1 and Tier-2, that is the entropy coder and the optimized rate control part, has been also completed. Last but not least, we establish a hardware/software co-operation framework for the entire JPEG2000 system. Through this framework, the JPEG2000 system can be operated more efficiently. It is also suitable for fast prototyping and demonstration for all digital signal processing designs.
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