A Spread Spectrum Clock Generator Based on a Sigma-Delta Modulated Phase-Locked Loop
碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === In communicating applications, narrow channel spacing is necessary to efficiently utilize the available frequency spectrum, and fast switching from one channel to another is necessary for high-data rates. One way to satisfy this requirement is to use...
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ndltd-TW-091NTU004280022016-06-20T04:15:45Z http://ndltd.ncl.edu.tw/handle/21067640765497298515 A Spread Spectrum Clock Generator Based on a Sigma-Delta Modulated Phase-Locked Loop 使用三角積分調變鎖相迴路製作之展頻時脈產生器 Ling-Yi Chang 張玲誼 碩士 國立臺灣大學 電子工程學研究所 91 In communicating applications, narrow channel spacing is necessary to efficiently utilize the available frequency spectrum, and fast switching from one channel to another is necessary for high-data rates. One way to satisfy this requirement is to use a fractional-N phase-locked-loop (PLL) architecture. But one major disadvantage of the fractional-N PLLs is the generation of high tones at multiples of the channel spacing. The use of digital sigma-delta modulation techniques in the fractional-N PLL can eliminate spurs. In today’s computer systems, better efficiency and faster speed are demanded. As operating at high frequencies, currents and voltages present in the circuits and the signal traces lead to greater electro-magnetic interference (EMI). There are many methods to reduce EMI. Among these solutions, spread spectrum clocking technique is the simplest and the most efficient one. It also offers the best immunity with respect to process variations. Spread spectrum clocking technique is a special case of frequency modulation. The basic idea of spread spectrum clocking is to slightly modulate the frequency of clock signals and the energy of the signals will be dispersed to a controllable small range. With spread spectrum modulation, the energy peak of every harmonic component in the spectrum is reduced. Accordingly, spread spectrum clocking can offer low EMI signals. This thesis provides an investigation into the fractional-N frequency synthesis and its application of the spread spectrum clock generation. The fractional-N PLL is fabricated in a standard 0.35um CMOS technology. The digital sigma-delta modulator and the spread spectrum modulation are implemented in field programmable gate array (FPGA). The experimental results show that the fractional-N frequency synthesizer and the spread spectrum clock generator do work. Shen-Iuan Liu 劉深淵 2003 學位論文 ; thesis 68 en_US |
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碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === In communicating applications, narrow channel spacing is necessary to efficiently utilize the available frequency spectrum, and fast switching from one channel to another is necessary for high-data rates. One way to satisfy this requirement is to use a fractional-N phase-locked-loop (PLL) architecture. But one major disadvantage of the fractional-N PLLs is the generation of high tones at multiples of the channel spacing. The use of digital sigma-delta modulation techniques in the fractional-N PLL can eliminate spurs.
In today’s computer systems, better efficiency and faster speed are demanded. As operating at high frequencies, currents and voltages present in the circuits and the signal traces lead to greater electro-magnetic interference (EMI). There are many methods to reduce EMI. Among these solutions, spread spectrum clocking technique is the simplest and the most efficient one. It also offers the best immunity with respect to process variations.
Spread spectrum clocking technique is a special case of frequency modulation. The basic idea of spread spectrum clocking is to slightly modulate the frequency of clock signals and the energy of the signals will be dispersed to a controllable small range. With spread spectrum modulation, the energy peak of every harmonic component in the spectrum is reduced. Accordingly, spread spectrum clocking can offer low EMI signals.
This thesis provides an investigation into the fractional-N frequency synthesis and its application of the spread spectrum clock generation. The fractional-N PLL is fabricated in a standard 0.35um CMOS technology. The digital sigma-delta modulator and the spread spectrum modulation are implemented in field programmable gate array (FPGA). The experimental results show that the fractional-N frequency synthesizer and the spread spectrum clock generator do work.
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author2 |
Shen-Iuan Liu |
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Shen-Iuan Liu Ling-Yi Chang 張玲誼 |
author |
Ling-Yi Chang 張玲誼 |
spellingShingle |
Ling-Yi Chang 張玲誼 A Spread Spectrum Clock Generator Based on a Sigma-Delta Modulated Phase-Locked Loop |
author_sort |
Ling-Yi Chang |
title |
A Spread Spectrum Clock Generator Based on a Sigma-Delta Modulated Phase-Locked Loop |
title_short |
A Spread Spectrum Clock Generator Based on a Sigma-Delta Modulated Phase-Locked Loop |
title_full |
A Spread Spectrum Clock Generator Based on a Sigma-Delta Modulated Phase-Locked Loop |
title_fullStr |
A Spread Spectrum Clock Generator Based on a Sigma-Delta Modulated Phase-Locked Loop |
title_full_unstemmed |
A Spread Spectrum Clock Generator Based on a Sigma-Delta Modulated Phase-Locked Loop |
title_sort |
spread spectrum clock generator based on a sigma-delta modulated phase-locked loop |
publishDate |
2003 |
url |
http://ndltd.ncl.edu.tw/handle/21067640765497298515 |
work_keys_str_mv |
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