| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 91 === As multimedia technologies improve, the use of digital still images has proliferated on the network. Reliable and efficient transmission and storage of encoded images have been a great concern of the industry. The International Standards Organization has established its next-generation still image compression standard, i.e. JPEG2000. It not only provides better rate-distortion performance, but also provides subjective image quality superior to JPEG. It also specifies many functionalities not found in the old standard. In this thesis, we propose an 8-pixel context forma-tion architecture for the new standard. When compared to the conven-tional architecture, ours increases the context formation throughput by 90%. It also doubles the performance of arithmetic encoding. The archi-tecture is implemented using a CMOS 0.35 μm 1P4M process. The chip area is 3.12 3.12 . It takes 0.461 seconds to encode a 1536 1536 image of Lena in 24-bit RGB when using a single arithmetic encoder (AE) operating at 100 MHz. If three AEs are employed, it takes only 0.233 seconds. It finishes the encoding of 30 frames of 512 512 image of Lena in YCbCr’s 4 : 2 : 0 in 0.768 seconds with one AE and in 0.393 seconds with three AEs. Therefore, the chip meets the motion JPEG2000 standard.
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