The Design of Switched-Capacitor Low-pass Filter for High Resolution Delta-Sigma D/A Converter

• Main Author: 張宮槐
• Other Authors: 劉萬榮
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/70047872620264914458

碩士 === 國立海洋大學 === 電機工程學系 === 91 === In this thesis, a switched-capacitor filter is designed for stereo applications. The specification is set with resolution of 16-bit and signal bandwidth of 24KHz. The whole circuit includes an one-bit digital-to-analog converter and low-pass filter. One-bit digital-to-analog converter is a single-end to fully differential converter which is fed by the input bit stream. It is followed by the low-pass filter. The realized low-pass filter is composed by the cascade of a third-order switched capacitor (SC) section and a first-order RC active section. The third-order SC filter is composed by the cascade of second-order (SC) filter and first-order (SC) filter. The use of third-order SC filter guarantees a good accuracy in the frequency and reduces the effects of the bit-stream nonidealities (like clock jitter and inaccurate edges). The first-order continuous-time filter allows the smoothing of SC filter output signal and accomplishes the final fully differential to singled-end transformation. The whole filter is simulated by MATLAB first. It is possible to gain loss (-3dB) at 50kHz. The switched-capacitor filter’s signal-to-noise ratio is over 71 dB, that is simulated with HSPICE. Finally, signal-to-noise ratio from the variation of input signal frequency would be analyzed and observe their relationship. The SC filter sample rate is 6.144MHz, the power supply is 3V. The fabrication technology is TSMC 0.25um 1P5M technology for SC filter.