A Novel Embedded EEPROM Using Trench Floating Gate
碩士 === 國立清華大學 === 電子工程研究所 === 91 === This study proposes a new kind of single poly EEPROM. The process steps and operation voltage of this structure are within tolerated CMOS logic process, which could apply to embedded memory. The differences between the new single poly trench...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25697089954972169698 |
| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 91 === This study proposes a new kind of single poly EEPROM. The process steps and operation voltage of this structure are within tolerated CMOS logic process, which could apply to embedded memory.
The differences between the new single poly trench floating gate EEPROM and the conventional devices are vertical trench floating gate using trench silicon technology and high coupling ratio using a deep n-well implant. The operation mechanisms of the new proposed device are channel hot carrier injection and drain-side FN tunneling. The best advantage of the new memory device is the high scale down ability.
This study discusses the device parameter which influence device characteristics by simulation analysis and design the optimum device. This work makes a comprehensive comparison with conventional single poly embedded flash or EEPROM. The new proposed device has the high implement ability on CMOS logic process and smaller area. This study could provide embedded memory a practical way.
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