Hierarchical pipeline insertion algorithm

• Main Authors: Jyun-Yi Yang, 楊駿毅
• Other Authors: Allen C.-H. Wu
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/33678909009119879728

碩士 === 國立清華大學 === 資訊工程學系 === 91 === Achieving high performance is one of the major goals of VLSI designs. The pipeline architecture is widely used for high-performance processor designs. The pipeline architecture can greatly reduce the circuit timing. The other goal of VLSI designs is to reduce the design area and cost. However, it’s hard to achieve a high-performance and low-cost design at the same time. In this thesis, we present an automatic pipeline insertion algorithm using retiming algorithm for inserting pipelines to a circuit such that the given timing constraint is satisfied while minimizing the overall area cost. Experimental results are reported to demonstrate the effectiveness of the algorithm.