The design and implementation of security and networking co-processors for high performance SoC applications

碩士 === 國立中山大學 === 資訊工程學系研究所 === 91 === With the development of Internet, there are more and more applications around us are connected tightly with it. Security of network is important. This thesis will follow OSI 7-layers architecture, which defined by ISO, to propose several hardware improvement ap...

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Bibliographic Details
Main Authors:	Kuo-huang Chung, 鍾國煌
Other Authors:	Ing-Jer Huang
Format:	Others
Language:	zh-TW
Published:	2003
Online Access:	http://ndltd.ncl.edu.tw/handle/84744382782374627716

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spelling	ndltd-TW-091NSYS53920052016-06-22T04:20:46Z http://ndltd.ncl.edu.tw/handle/84744382782374627716 The design and implementation of security and networking co-processors for high performance SoC applications 針對高效能SoC應用之資訊安全及網路協同處理器設計與實作 Kuo-huang Chung 鍾國煌碩士國立中山大學資訊工程學系研究所 91 With the development of Internet, there are more and more applications around us are connected tightly with it. Security of network is important. This thesis will follow OSI 7-layers architecture, which defined by ISO, to propose several hardware improvement approaches of network security. In data-link layer, we improve performance of CRC calculation with parallel CRC calculation, such that a 32-bit data can be finished using CRC calculation in one cycle. In network layer and transport layer, bit-oriented instruction set has good performance for processing packet header. In application, we implement DES and AES algorithm in hardware. We integrate all hardware module with ARM7TDMI coprocessor’s interface. Finally, we download integrated circuit into Xilinx XCV2000E chip to observe its demo to verify it. Ing-Jer Huang 黃英哲 2003 學位論文 ; thesis 104 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立中山大學 === 資訊工程學系研究所 === 91 === With the development of Internet, there are more and more applications around us are connected tightly with it. Security of network is important. This thesis will follow OSI 7-layers architecture, which defined by ISO, to propose several hardware improvement approaches of network security. In data-link layer, we improve performance of CRC calculation with parallel CRC calculation, such that a 32-bit data can be finished using CRC calculation in one cycle. In network layer and transport layer, bit-oriented instruction set has good performance for processing packet header. In application, we implement DES and AES algorithm in hardware. We integrate all hardware module with ARM7TDMI coprocessor’s interface. Finally, we download integrated circuit into Xilinx XCV2000E chip to observe its demo to verify it.
author2	Ing-Jer Huang
author_facet	Ing-Jer Huang Kuo-huang Chung 鍾國煌
author	Kuo-huang Chung 鍾國煌
spellingShingle	Kuo-huang Chung 鍾國煌 The design and implementation of security and networking co-processors for high performance SoC applications
author_sort	Kuo-huang Chung
title	The design and implementation of security and networking co-processors for high performance SoC applications
title_short	The design and implementation of security and networking co-processors for high performance SoC applications
title_full	The design and implementation of security and networking co-processors for high performance SoC applications
title_fullStr	The design and implementation of security and networking co-processors for high performance SoC applications
title_full_unstemmed	The design and implementation of security and networking co-processors for high performance SoC applications
title_sort	design and implementation of security and networking co-processors for high performance soc applications
publishDate	2003
url	http://ndltd.ncl.edu.tw/handle/84744382782374627716
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The design and implementation of security and networking co-processors for high performance SoC applications

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