| Summary: | 碩士 === 國立中山大學 === 資訊工程學系研究所 === 91 === With the development of Internet, there are more and more applications around us are connected tightly with it. Security of network is important. This thesis will follow OSI 7-layers architecture, which defined by ISO, to propose several hardware improvement approaches of network security. In data-link layer, we improve performance of CRC calculation with parallel CRC calculation, such that a 32-bit data can be finished using CRC calculation in one cycle. In network layer and transport layer, bit-oriented instruction set has good performance for processing packet header. In application, we implement DES and AES algorithm in hardware. We integrate all hardware module with ARM7TDMI coprocessor’s interface. Finally, we download integrated circuit into Xilinx XCV2000E chip to observe its demo to verify it.
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