| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 91 === This thesis conducts a high performance of Phase Locked Loops (PLLs) in GSM band. It is assumed that the modulated technology to send data with high frequency but it can not transmit as long distance in wireless environment and the demodulation technology in receiver, is restored original data from RF front-end to baseband. From the wireless system, the channel band limited, we should be to solve the band limited by the multiplex technology only.
In the wireless communication, we must have a high stable local oscillator as show in conventional super heterodyne to restore the original data. In this thesis, we have been studied and implemented the high performance Phase Locked Loops, which will be to replace the local oscillator in wireless communication system. For the results, we first have a program control with single chip as 8051 to control the channel band, and then to get the short locked time and the low phase noise for our optimum design.
For short locked time, we assume that the system is no noise interference to calculate as following mathematical model and simulate by matlab. In addition, we get the transient response by the unit step input for first order and second order loop filter as frequency response. Then, it is easy to solve the discussion results:
(1)Can find the phase locked still as PLLs work normally.
(2)Can find the optimum parameter for PLLs as short locked time.
For the low noise, we can assume that the system is a linear to analyze the equivalent block diagram and to get the total response for PLLs.
In our study, we realize the multi-channel for PLLs with IC SP8853 and meet the specification of GSM. We have the results by simulation with the wireless platform and results show an excellent performance. In particular, we get an optimum design flow to t fast realization for low cost and non-complexity.
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