Design and Evaluation of a Low-Power On-Chip Network Based on Dynamic Voltage Scaling with Links

• Main Authors: Chao-Hung Chang, 張兆宏
• Other Authors: Hsin-Chou Chi
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/07749389947251963358

碩士 === 國立東華大學 === 資訊工程學系 === 91 === In the future, systems-on-chip employing an on-chip network is evolving toward complex heterogeneous components made of many macro-cells (e.g., processors, DSPs, memory, controllers, and custom logic). The bandwidth of a link has been increasing fast in on-chip networks. This can lead to huge power consumption as the demand for network bandwidth increases. Hence, we need to seriously consider power efficiency in an intra-chip interconnect. Additionally, it is important to realize that the traffic on a transmitting link may change dynamically, and thus that supply voltage needs not be kept at its peak at all time. Therefore, we propose an architecture for low-power transmission links in an on-chip network. Our scheme uses the idea of dynamic voltage scaling for intra-chip communications. According to the network traffic, supply voltage and operating frequency of links are dynamically adjusted to minimize power consumption. We have implemented a cycle-based simulator to evaluate the power-performance for our architecture. The evaluation of our link architecture helps strike a good balance between power saving and latency-throughput penalty. The link architecture consists of a power level controller, adaptive power supply regulator, link utilization calculator, and link buffer utilization calculator. We have implemented the major components for our architecture with a VLSI design. Our results show that the proposed link design is effective and consumes significantly less power.