Design and Evaluation of a Low-Power On-Chip Network Based on Dynamic Voltage Scaling with Links
碩士 === 國立東華大學 === 資訊工程學系 === 91 === In the future, systems-on-chip employing an on-chip network is evolving toward complex heterogeneous components made of many macro-cells (e.g., processors, DSPs, memory, controllers, and custom logic). The bandwidth of a link has been increasing fast in on-chi...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/07749389947251963358 |