| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 91 === For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models are built with lookup tables. However, building the power models with lookup tables may become infeasible for large circuits because the table size would increase exponentially to meet the accuracy requirement. Furthermore, because it is hard to control the distribution of average output transition density, those approaches suffer problems with unpredicted characterization time to fill the lookup tables.
In this thesis, we propose a novel power modeling approach for complex circuits by using neural networks to learn the relationship between power dissipation and input/output characteristic vector during simulation. Our neural power model has very low complexity such that this power model can be used for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear power distributions. Unlike the power characterization process in traditional approaches, our characterization process is very simple and straightforward. More importantly, using the neural power model for power estimation does not require any transistor-level or gate-level description of the circuits, which is very suitable for IP protection. The experimental results have shown that the estimations are accurate and efficient for different test sequences with wide range of input distributions.
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