| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 91 ===
The full of vitality multimedia communications development has increased dramatically 3C industry in the world. Therefore practical applications, tradition ASIC system cannot meet the rapidly and vary development and design integrated. However, standard CPU also cannot meet the rapidly application. Since the system design more complexity and time-to-market pressure, the platform-based design methodology has approached.
In this thesis, we develop a SOPC platform-based design environment for multimedia communications. We adopt the Altera APEX20K200E484-2X device. The JPEG compression is performed on software method in the embedded processor. First, we embed a Nios processor in FPGA (Field Programmable Gate Array). Second, we feed the image data with Nios processor by CMOS sensor. The compressed image data transports to client user by Ethernet daughter board. In this task, we successfully complete the JPEG compression by the Nios processor and web server system. The raw image data is stored in the flash memory. Afterward, the embedded processor can be fetched the raw image data from the flash memory. The compressed image data is stored in SRAM memory. The format of the JPEG image will be transformed to the client by the Ethernet daughter board. Eventually, the user can be accessed the compressed image data through by browser.
|
|---|
