A New Design and Verification ofStream Cipher Module UsingFPGA Device
碩士 === 國立中央大學 === 電機工程研究所 === 91 === The thesis presents a new design of stream cipher encryption chip and makes use of S.P.N.(Substitution Permutation Networks) as second stage to enhance backwards of conventional cipher. The cipher chooses CBC(Cipher Block Chaining mode) as operation mode to b...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/82842629182785030934 |
| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 91 ===
The thesis presents a new design of stream cipher encryption chip and makes use of S.P.N.(Substitution Permutation Networks) as second stage to enhance backwards of conventional cipher. The cipher chooses CBC(Cipher Block Chaining mode) as operation mode to be synchronization control between encryption and decryption devices.
Adopting “bottom-up” design is used to improve performances. The new design is aimed at f function selection. The chip is a microprocessor peripheral device and could be useful for network devices. They use an 8-bit user-specified key to encrypt and decrypt 8-bit blocks of data.
The chip can be used in real time applications and variety of Electronic Funds Transfer applications. In order to reduce the I/O pins, the shift registers are designed as parallel process.
By making use of VHDL’92, Synplify, and Maxplus9.6 □for designing. Synthesizing and simulating is prepared to realize the chip. Field Programmable Gate Arrays (FPGAs) are chosen as our target hardware environment and verification function with board. The design of this chip for area requires 169 logic cells. The maximum operating clock is 100 MHz and the corresponding data throughput is about 80 Mbps.
|
|---|