5.2GHz CMOS RF Receiver Frond-end Circuits Design

• Main Authors: chi-wei liang, 梁志維
• Other Authors: none
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/09787132705552929083

碩士 === 國立中央大學 === 電機工程研究所 === 91 === The radio frequency (RF) front-end of the wireless communication systems such as cellular phones, cordless phone, and personal communication system (PCS) are almost implemented by GaAs or Bipolar technologies due to their good performance in high frequency. However, the rapid advancement and scaling of the size done in CMOS technology, which now offers higher unity current gain cut off frequency (fT) and maximum operatng frequency (fmx), has been comparaed with GaAs and Bipolar. A RF frond-end circuit fabricated in TSMC 0.18um CMOS technology is presented in this thesis. It is suitable for 5-GHz ISM band. This frond-end circuit adopted a low-noise amplifier with single input. A symmetric passive balun is included in the mixer circuit to implement the double-balance mixer. The 6-stage polyphase filter and high linearity inter-stage buffer reject the image band more than 60dB. The overall receiver consumes 30mW with 1.8V supply voltage. The local signal is supplied by a high accuracy quadrature synchronous oscillator. This oscillator is locked by using 1/9 output frequency signal. This synchronous oscillator simplifies the frequency generator design.