| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系 === 91 === The discrete wavelet transform (DWT) technique has been widely used in signal processing and image processing. Since the DWT coefficients have the property of energy conservation in the low frequency part, it is suitable for data compression. In the recent industry standard, DWT has replaced DCT which is a main approach in image compression in JPEG2000 and MPEG4.
Due to the drawback, the thesis focuses on the hardware architectures of 1-layer 1- dimensional DWT, multi-layer 1-dimensional DWT and Multi-layer 2-dimensional DWT which are the standard of JPEG2000. Based on the architecture, DWT and the inverse discrete wavelet transform (IDWT) can be integrated easily. Furthermore we can use the module design concept to implement DWT by different hardware architectures.
Moreover, in the thesis, we use two different architectures to implement the multi-layer 1-dimensional DWT. Besides, accompanied with “2D-controller”the multi-layer 1-dimensional DWT can be adopted in multi-layer 2-dimension DWT hardware architecture.
Consequently, the gate level simulation and P&R are done with Synopsys and Avant! tools. The chip has advantages in the ability of image processing, execution time and chip area.
|
|---|
