| Summary: | 碩士 === 國立交通大學 === 電信工程系 === 91 === The IEEE 802.11a standard was defined in order to support the demand of high data rate WLANs. It adopts OFDM modulation and provides data rates from 6Mbps to 54Mbps. In this thesis, we propose an IEEE 802.11a baseband receiver architecture according to its specified packet format. The receiver includes several functional parts: packet detection, symbol timing estimation, coarse and fine carrier frequency offset estimation, channel estimation, phase offset estimation and data detection. We describe the operation principles and the algorithms of each part in details, and we try to make a good tradeoff between system performance and computational complexity. In order to verify the performance of the receiver, computer simulations are conducted under different channel conditions. Our simulation results include the performance of each functional part and the BER and PER of the whole system. From the simulation results, we can determine which parts are more critical to the whole system performance than others. Finally, we draw a conclusion and comment on possible future research directions.
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