A Study on Process Related Reliabilities of CMOS Transistors with Ultra-Thin Gate Dielectrics

• Main Authors: Da-Yuan Lee, 李達元
• Other Authors: Tiao-Yuan Huang
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/70535268049901942614

博士 === 國立交通大學 === 電子工程系 === 91 === The reliability of gate dielectric has been an important issue for ultra large scale integrated (ULSI) circuits, especially as the aggressive downscaling of CMOS technology continues. In this dissertation, we have investigated reliability issues regarding soft breakdown (SBD) and negative-bias-temperature instability (NBTI) for nanometer CMOS devices with ultra-thin gate dielectrics. To start with, post-breakdown current-voltage characteristics of MOS devices with ultra-thin gate oxide have been carefully studied. New breakdown modes were identified. Specifically, it was found that typical soft-breakdown mode induced in oxide thinner than 3 nm is actually quite different from that in oxide thicker than 3 nm. Based on these findings, we have proposed a model to explain the evolution of different breakdown modes. The model takes into consideration the thermal runaway process at the breakdown moment, and is substantiated by a number of experimental findings. Impacts of each breakdown mode on device switching behavior are also discussed. Next, the effects of plasma charging on the NBTI of p-channel metal-oxide semiconductor (PMOS) transistors were explored in this work. It is clearly shown that the threshold voltage shift during negative bias-temperature stressing (BTS) could be enhanced by plasma charging damage. More importantly, we also found that electron trappings are aggravated by plasma charging, even on virgin devices with large antenna area ratios prior to negative BTS. Our charge pumping current measurements confirm that the interface-state density is increased for devices with large antennas, both before and after the BTS. Based on these findings, we also proposed that the NBTI characterization can be used as a sensitive method for characterizing the antenna effects in devices with ultra-thin gate oxide, which is particularly attractive in light of the fact that conventional indicators are becoming inadequate as oxide is scaled down. Furthermore, the effects of poly-Si gate doping type and species as well as thermal treatments on NBTI of p-channel MOSFET were investigated in this work. It is found that devices with n+ poly-Si gate depict smaller threshold voltage shift after negative BTS, compared to their p+-poly-Si-gated counterparts. By carefully controlling the thermal budget to suppress boron penetration, NBTI can be reduced by fluorine incorporation in p+-poly-Si-gated devices. The NBTI is found to be aggravated in devices subjected to H2 post-metal-annealing (PMA), highlighting the important role of hydrogen bonds. The NBTI of pMOSFETs with ultra-thin gate dielectric is also characterized in this thesis. Proper scaling of gate oxide thickness is essential for low supply voltage and high driving capability, the ultra-thin nitride-related materials are the most promising candidates for replacing silicon oxide as a gate dielectric for sub-100nm node. A new mechanism due to holes trapping in the nitride/oxide (N/O) stack during negative BTS is identified. The Vth shift caused by negative BTS is found to recover after negative BTS stressing for either N/O stack or nitrided oxide. The Vth recovery phenomenon is caused by trapped holes relaxing during long-term break. Such mechanism becomes more significant as the channel length is scaled down, and could be important for future high-k gate dielectric applications. Finally, we have investigated the effects of HF etching on the integrity of ultra-thin oxides in dual gate oxide (DGO) CMOS technologies. We found that both the HF concentration in the etching solution and the over etching (OE) time are important parameters that greatly affect the device performance and reliability. Our results indicate that, with a proper over etching period, using a “less diluted” HF solution results in better ultra-thin gate oxides in terms of reduced defect density, improved device performance and reliability, compared to using “diluted” HF solution. It is also found for the first time that time-dependent dielectric breakdown (TDDB) and NBTI immunity for PMOSFETs is improved by using “less diluted” HF solution.