Pipelining Techniques for Energy-Aware Datapath Designs
碩士 === 國立交通大學 === 電子工程系 === 91 === Recently, portable multimedia and wireless products dominate the consumer electronics market, which require simultaneous power and performance optimizations. The real-time computations make traditional static low power techniques less efficient, because...
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ndltd-TW-091NCTU04281242016-06-22T04:14:26Z http://ndltd.ncl.edu.tw/handle/29093986058812516235 Pipelining Techniques for Energy-Aware Datapath Designs 具能量感知之資料路徑的管線化設計技巧 Chien-Hung Lin 林建宏 碩士 國立交通大學 電子工程系 91 Recently, portable multimedia and wireless products dominate the consumer electronics market, which require simultaneous power and performance optimizations. The real-time computations make traditional static low power techniques less efficient, because the architecture must satisfy the worst-case performance requirements. Power (or energy) aware systems are able to scale the power dissipation with the changing conditions and quality, and thus become attractive in low power design community. This thesis presents a novel pipelining scheme to enhance the power- (or energy-) awareness of datapath designs, which activates the pipeline registers only when necessary. A datum bypasses the registers when the operation is free of race from the succeeding datum, and when the glitch is minimal, while the unused pipeline registers are clock-gated to reduce energy dissipation. The proposed scheme is able to exploit much more dynamic behaviors of an application at finer granularity of the datapath designs than other low power techniques, such as changing the supplying voltages at the run time. Moreover, our scheme has identical input-to-output latency for all operation modes, which effectively simplifies the system integration. In our simulation, the proposed scheme can reduce up to 70% energy dissipation in normal pipelines or improve 15%~36% energy of previous clock gating methods. Moreover, for identical loads, say 3,000 multiplications, the simulation result shows that the energy dissipation in our on-demand registered pipelined multiplier decreases as the allowed processing time increases. Therefore, we develop an energy-aware scheduling algorithm to optimize the energy dissipation of our multiplier. Our simulation result shows that the proposed optimal scheduling saves about 20% energy in the DCT example using list scheduling. Chein-Wei Jen 任建葳 2003 學位論文 ; thesis 80 en_US |
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碩士 === 國立交通大學 === 電子工程系 === 91 === Recently, portable multimedia and wireless products dominate the consumer electronics market, which require simultaneous power and performance optimizations. The real-time computations make traditional static low power techniques less efficient, because the architecture must satisfy the worst-case performance requirements. Power (or energy) aware systems are able to scale the power dissipation with the changing conditions and quality, and thus become attractive in low power design community.
This thesis presents a novel pipelining scheme to enhance the power- (or energy-) awareness of datapath designs, which activates the pipeline registers only when necessary. A datum bypasses the registers when the operation is free of race from the succeeding datum, and when the glitch is minimal, while the unused pipeline registers are clock-gated to reduce energy dissipation. The proposed scheme is able to exploit much more dynamic behaviors of an application at finer granularity of the datapath designs than other low power techniques, such as changing the supplying voltages at the run time. Moreover, our scheme has identical input-to-output latency for all operation modes, which effectively simplifies the system integration. In our simulation, the proposed scheme can reduce up to 70% energy dissipation in normal pipelines or improve 15%~36% energy of previous clock gating methods.
Moreover, for identical loads, say 3,000 multiplications, the simulation result shows that the energy dissipation in our on-demand registered pipelined multiplier decreases as the allowed processing time increases. Therefore, we develop an energy-aware scheduling algorithm to optimize the energy dissipation of our multiplier. Our simulation result shows that the proposed optimal scheduling saves about 20% energy in the DCT example using list scheduling.
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Chein-Wei Jen |
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Chein-Wei Jen Chien-Hung Lin 林建宏 |
author |
Chien-Hung Lin 林建宏 |
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Chien-Hung Lin 林建宏 Pipelining Techniques for Energy-Aware Datapath Designs |
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Chien-Hung Lin |
title |
Pipelining Techniques for Energy-Aware Datapath Designs |
title_short |
Pipelining Techniques for Energy-Aware Datapath Designs |
title_full |
Pipelining Techniques for Energy-Aware Datapath Designs |
title_fullStr |
Pipelining Techniques for Energy-Aware Datapath Designs |
title_full_unstemmed |
Pipelining Techniques for Energy-Aware Datapath Designs |
title_sort |
pipelining techniques for energy-aware datapath designs |
publishDate |
2003 |
url |
http://ndltd.ncl.edu.tw/handle/29093986058812516235 |
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