| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 91 === Recently, portable multimedia and wireless products dominate the consumer electronics market, which require simultaneous power and performance optimizations. The real-time computations make traditional static low power techniques less efficient, because the architecture must satisfy the worst-case performance requirements. Power (or energy) aware systems are able to scale the power dissipation with the changing conditions and quality, and thus become attractive in low power design community.
This thesis presents a novel pipelining scheme to enhance the power- (or energy-) awareness of datapath designs, which activates the pipeline registers only when necessary. A datum bypasses the registers when the operation is free of race from the succeeding datum, and when the glitch is minimal, while the unused pipeline registers are clock-gated to reduce energy dissipation. The proposed scheme is able to exploit much more dynamic behaviors of an application at finer granularity of the datapath designs than other low power techniques, such as changing the supplying voltages at the run time. Moreover, our scheme has identical input-to-output latency for all operation modes, which effectively simplifies the system integration. In our simulation, the proposed scheme can reduce up to 70% energy dissipation in normal pipelines or improve 15%~36% energy of previous clock gating methods.
Moreover, for identical loads, say 3,000 multiplications, the simulation result shows that the energy dissipation in our on-demand registered pipelined multiplier decreases as the allowed processing time increases. Therefore, we develop an energy-aware scheduling algorithm to optimize the energy dissipation of our multiplier. Our simulation result shows that the proposed optimal scheduling saves about 20% energy in the DCT example using list scheduling.
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