5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11a
碩士 === 國立交通大學 === 電子工程系 === 91 === In this thesis, a dual gain mode direct-conversion receiver front-end under 802.11a specification is designed and implemented by UMC 0.18μm 1P6M process. Giga-solution RF component models, SPIL QFN series package, and FR-4 printed-circuit-board are adopt...
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2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09206613423689949555 |
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ndltd-TW-091NCTU04281222016-06-22T04:14:26Z http://ndltd.ncl.edu.tw/handle/09206613423689949555 5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11a 5-GHzCMOS雙增益模式之IEEE802.11a前端接收器設計 Wei-Cheng Tang 唐偉烝 碩士 國立交通大學 電子工程系 91 In this thesis, a dual gain mode direct-conversion receiver front-end under 802.11a specification is designed and implemented by UMC 0.18μm 1P6M process. Giga-solution RF component models, SPIL QFN series package, and FR-4 printed-circuit-board are adopted for the implementation and assembly. The front-end implementation includes a LNA, a mixer, a high pass filter, and a baseband amplifier. The measurement result indicates the voltage gain to be 27.4dB and 14.3dB under high and low gain mode individually, and IIP3 is measured as -12.8dBm and +4.5dBm. IIP2 is measured as -13.5dBm, and noise figure is 8.5dB. 溫瓌岸 2003 學位論文 ; thesis 125 en_US |
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en_US |
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碩士 === 國立交通大學 === 電子工程系 === 91 === In this thesis, a dual gain mode direct-conversion receiver front-end under 802.11a specification is designed and implemented by UMC 0.18μm 1P6M process. Giga-solution RF component models, SPIL QFN series package, and FR-4 printed-circuit-board are adopted for the implementation and assembly. The front-end implementation includes a LNA, a mixer, a high pass filter, and a baseband amplifier. The measurement result indicates the voltage gain to be 27.4dB and 14.3dB under high and low gain mode individually, and IIP3 is measured as -12.8dBm and +4.5dBm. IIP2 is measured as -13.5dBm, and noise figure is 8.5dB.
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| author2 |
溫瓌岸 |
| author_facet |
溫瓌岸 Wei-Cheng Tang 唐偉烝 |
| author |
Wei-Cheng Tang 唐偉烝 |
| spellingShingle |
Wei-Cheng Tang 唐偉烝 5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11a |
| author_sort |
Wei-Cheng Tang |
| title |
5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11a |
| title_short |
5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11a |
| title_full |
5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11a |
| title_fullStr |
5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11a |
| title_full_unstemmed |
5-GHz CMOS Dual Gain Mode Receiver Front End Design for IEEE 802.11a |
| title_sort |
5-ghz cmos dual gain mode receiver front end design for ieee 802.11a |
| publishDate |
2003 |
| url |
http://ndltd.ncl.edu.tw/handle/09206613423689949555 |
| work_keys_str_mv |
AT weichengtang 5ghzcmosdualgainmodereceiverfrontenddesignforieee80211a AT tángwěizhēng 5ghzcmosdualgainmodereceiverfrontenddesignforieee80211a AT weichengtang 5ghzcmosshuāngzēngyìmóshìzhīieee80211aqiánduānjiēshōuqìshèjì AT tángwěizhēng 5ghzcmosshuāngzēngyìmóshìzhīieee80211aqiánduānjiēshōuqìshèjì |
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