On Hierarchical Submodule Extraction for Transistor Netlists
碩士 === 國立交通大學 === 電子工程系 === 91 === The growing of modern IC design complexity leads the consistency check and design verification during every level in design flow to be an important and challenged issue. In this thesis, we propose an efficient approach to rebuild the hierarchical level f...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65596796604708642129 |