On Hierarchical Submodule Extraction for Transistor Netlists

• Main Authors: Yi-Wei Lin, 林詣偉
• Other Authors: Jing-Yang Jou
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/65596796604708642129

碩士 === 國立交通大學 === 電子工程系 === 91 === The growing of modern IC design complexity leads the consistency check and design verification during every level in design flow to be an important and challenged issue. In this thesis, we propose an efficient approach to rebuild the hierarchical level from low level circuits. Our approach is based on the structure equivalent expansion algorithm to find repeated submodules in every circuit level to reconstruct circuit hierarchy. Without any addition library information, our approach is quite efficient in both time and space complexities by using only flatten netlists. The experiments on many real circuits containing combinational, sequential, and memory circuits show that our approach can rebuild most circuit hierarchical levels and also reduce the verification effort of the circuits.