| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 91 === As the IC fabrication technology advances, the need for high-bandwidth and low-latency inter-chip data transfer in short-distance applications has also increased. Therefore, it has led to widespread use of point-to-point links. The thesis describes the design of a high-speed serial link I/O interface. The transmission data rate is targeted at 400Mbps.
The transceiver used a phase-locked loop (PLL) as a timing circuit to provide multi-phases output for the 4-to-1 multiplexer in transmitter and 3 times oversampling in receiver. The PLL, employing charge-pump, consists of six-stage differential ring oscillator to provide four phases for the transmitter and twelve phases for the receiver. The input frequency of the PLL is 50MHz and output is 100MHz. The open-drain current mode data driver in transmitter uses current pulse generation circuits to provide large but short period current sources to enhance the transition of the transmitted data bit, therefore reducing the inter-symbol-interference effect. To recover the transmitted data stream correctly, the receiver adopts a digital feedback control loop. By using 3 times oversampling technique, the system could prevent the metastability problem in 2 times oversampling tracking system. The receiver also has the advantage of simple data selection logic and digital phase shifting mechanism, thus simplifying the hardware design and improving noise immunity. Finally, the recovered data stream is demultiplexed to the four parallel data channels, each with data rate of 100MHz.
The receiver is implemented in a 0.35-μm 1P4M CMOS process and the supply voltage is 3.3V. The measured rms and peak-to-peak jitter of the 100MHz output clock of the PLL are 16.57ps and 120ps, respectively.
|
|---|
