| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 91 === A design of 2.4GHz CMOS quadrature VCO and frequency divider and their applications in fractional-N frequency synthesizer is described in this thesis.
The proposed whole new quadrature generator is fabricated using a standard TSMC 0.25um CMOS process and has been measured completely. The measurement results of this chip meet the requirement that provides sufficient image rejection ratio in the most RF receiver architecture. A 1.5v 32/33 dual-modulus frequency divider is also presented in this thesis. It combines quadrature injection-locked frequency divider and phase switching technique to reduce power consumption. It works at frequency band 2.4~2.5GHz and consumes about 7mW.
A delta-sigma fractional-N frequency synthesizer including two blocks mentioned above is presented. This frequency synthesizer combines these two blocks and proves their functionality. This synthesizer introduces conventional deadzone-less PFD, conventional charge-pump, third order loop filter, proposed quadrature VCO, proposed quadrature injection-locked divider combining with phase switching technique and an all digital third order single bit delta-sigma modulator with mash3 delta-sigma modulator dithering input as fractional modulus generator.
|
|---|
