An Intelligent Hybrid Approach to Optimal Characterization of Nanoscale MOSFET Devices

• Main Authors: YEN-YU CHO, 卓彥羽
• Other Authors: JIANN-MEAN TAN
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/91309223450509530793

碩士 === 國立交通大學 === 資訊科學系 === 91 === Semiconductor model parameters extraction plays an important role between device foundries and integrated circuit (IC) design companies yet a bottleneck in microelectronics industry. Various compact models have been of great interest and studied for nanoscale metal-oxide-semiconductor field effect transistor (MOSFET) device simulation. The model parameters extraction intrinsically characterizes properties of designed and fabricated devices. It leads to a multidimensional optimization problem to be solved and extracted efficiently for the applications to very large scaled integrated (VLSI) circuit and system-on-a-chip (SoC) design. Different approaches, such as empirical, numerical, and statistical methods have been proposed to solve this problem. However, these approaches encounter serious problems in nanoscale MOSFET era, such as poor accuracy, time-consuming, ineffective extraction process, and lack the predict capacity in practical applications. In this work we present an intelligent hybrid system for BSIM4 model in nanoscale MOSFET model parameters extraction. This approach combines with the genetic algorithm, the numerical optimization, the neural network, and the empirical experiences has been proposed and successfully developed on a Linux based personal computer (PC) cluster system. First of all, the preprocess including empirical constrains and data reduction is performed to reduce massive computation depending on the continuity of the model. The genetic algorithm is then applied to extract a rough solution and the numerical optimization is functioned to obtain an further improved solution. The neural network is adopted for curves and physical quantities inspection, this procedure adjusts the evolutionary direction of genetic algorithm to enhance the extraction performance. After a set of parameters is found and a sensible search path is detected, the genetic algorithm keeps evolving the next generation until a set of optimal parameters reaches certain stopping criteria. Excellent accuracy has been obtained in several experiments for both the 90 nm and 130 nm NMOSFET devices in terms of IDS-VDS and IDS-VGS curves, and related physical quantities. Comparing to conventional approaches, the proposed methodology contained the advantage of both numerical and soft computing methods solves the extracting problem cost efficiently. The proposed extraction architecture significantly reduces the demand of time and enhances the working performance in the practice use, which is useful in VLSI circuit and SoC design.