| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 91 === ABSTRACT
The research of this thesis, “Phase Locked Loop based Frequency Synthesizer,” is focused on each subsystem circuit of the frequency synthesizer, such as the phase/frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the divider. The comparison of the characteristics between the subsystems has been done.
To design the frequency synthesizer, the behavior of the system is analyzed by using the mathematics tool, SIMULINK of MATLAB. The schematic of the circuit is simulated by using HSPICE with the parameters of TSMC 0.35μm 1P4M CMOS process model. Two kinds of voltage-controlled oscillators, which are consisted by fully differential delay cells, are used to simulate the performance of the frequency synthesizer.
The frequency synthesizer is demonstrated in TSMC 0.35μm 1P4M CMOS technology. The simulated results show that the maximum operation frequency is 400 MHz and the power consumption is 18 mW. The chip area including the test circuit and pads is 1.428 mm × 1.428 mm.
Keywords: phased locked loop (PLL), frequency synthesizer, phase/frequency detector, charge pump, loop filter, voltage-controlled oscillator, divider.
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