| Summary: | 碩士 === 國立暨南國際大學 === 資訊管理學系 === 91 === The research of this thesis deals with the collaborative planning problems in the IC manufacturing chains (ICMC).
Semiconductor industry has strived to differentiate their products and services with high add-on values from the competitors due to fierce global competition and very short product life cycles. The rapid fluctuating demand on IC products is critical to the operations of an individual lot within the ICMC. In addition to being capable of the most advanced semiconductor manufacturing technology to produce IC products of high quality, IC manufacturers have to timely deliver products to their customers with short cycle time. It is still a very challenging research topic for sound production
planning within IC manufacturing chains.
In this thesis, we propose a Highway Vehicle Allocation (HVA) model for integrated planning of IC manufacturing chains. For each lot in the ICMC, a production speed (in number of stages processed in a day) is tagged on it as its daily production
target. The speed of a lot can be dynamically changed or adjusted. The higher the speed is, the shorter cycle time it takes. As there are only limited resources at a time, a quota for each speed level is specified. Our objective of planning ICMC is to fulfill the customers' requirements in a just-in-time way, while satisfying all the speed quota limitation.
The ICMC planning problem is first formulated into an integer programming problem and solved by optimization methodologies of Lagrangian relaxation and minimum cost network flow algorithms. Numerical results indicate that this approach can generate
near-optimal solutions and is efficient in the application to the realistic problem. We also designate a test case to analyze the algorithmic sensitivity to explore the effect caused by the WIP profile.
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