| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === A BGA socket acts as an interface between the load board and the integrated circuit during the testing. The socket propagates signals through pogo pins, then the testing machine judges if the IC works or not. However, the performance of sockets decay with time. A process of socket modeling is needed to create a BGA socket model and, based on the model, to determine in what kind of conditions should the sockets or pogo pins must be replaced.
In this thesis, a BGA socket model is derived and used to predict the time domain performance. Time Domain Reflectometry (TDR) are applied to get the initial values of the model, then they are fine tuned to fit the measured results from the network analyzer, by using a high-frequency circuit simulator. Calibration kits and test-fixture have been made to simulate the conditions of open, short and through for real integrated circuits during the modeling process.
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