Design of A Dual Mode Turbo/Convolutional Codec IP

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === This Paper present a design process and result of a dual mode turbo/ convolutional codec IP. It is obvious that the IP we designed have two major function. One is the encoding and decoding of the turbo code and the other is the encoding and decoding of the con...

Full description

Bibliographic Details
Main Authors: U-Lin Hsu, 許毓霖
Other Authors: Jer-Min Jou
Format: Others
Language:en_US
Published: 2003
Online Access:http://ndltd.ncl.edu.tw/handle/85719571319605059493
id ndltd-TW-091NCKU5442182
record_format oai_dc
spelling ndltd-TW-091NCKU54421822016-06-22T04:14:02Z http://ndltd.ncl.edu.tw/handle/85719571319605059493 Design of A Dual Mode Turbo/Convolutional Codec IP 渦輪碼/迴旋碼雙模式編解碼器系統設計與實現 U-Lin Hsu 許毓霖 碩士 國立成功大學 電機工程學系碩博士班 91 This Paper present a design process and result of a dual mode turbo/ convolutional codec IP. It is obvious that the IP we designed have two major function. One is the encoding and decoding of the turbo code and the other is the encoding and decoding of the convolutional code. As the increasing opportunities of the data transfer of the modern digital or mobile communication, the reliability of the data transfer has become more and more important. Therefore, the FEC have played an very important role nowadays. The motivation of this paper is to design an IP which could provide the ability of error control. The turbo code is one of the most popular of the error correcting code at present due to its correct ability of the burst errors. Besides, the convolutional and turbo code are adapted in the 3G mobile communication standard.This is why we intend to design a dual mode IP with the convolutional and turbo codec. In this paper we introduce not only the conception and theorem but also the implementation of the IP. In the design process, we achieve software simulation of both two codec with C++ and then we implement it by Verilog. After the coding process with the verilog, we take use of the Xilinx foundation 4.1 to help us simulate the hardware we have designed. Jer-Min Jou 周哲民 2003 學位論文 ; thesis 111 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === This Paper present a design process and result of a dual mode turbo/ convolutional codec IP. It is obvious that the IP we designed have two major function. One is the encoding and decoding of the turbo code and the other is the encoding and decoding of the convolutional code. As the increasing opportunities of the data transfer of the modern digital or mobile communication, the reliability of the data transfer has become more and more important. Therefore, the FEC have played an very important role nowadays. The motivation of this paper is to design an IP which could provide the ability of error control. The turbo code is one of the most popular of the error correcting code at present due to its correct ability of the burst errors. Besides, the convolutional and turbo code are adapted in the 3G mobile communication standard.This is why we intend to design a dual mode IP with the convolutional and turbo codec. In this paper we introduce not only the conception and theorem but also the implementation of the IP. In the design process, we achieve software simulation of both two codec with C++ and then we implement it by Verilog. After the coding process with the verilog, we take use of the Xilinx foundation 4.1 to help us simulate the hardware we have designed.
author2 Jer-Min Jou
author_facet Jer-Min Jou
U-Lin Hsu
許毓霖
author U-Lin Hsu
許毓霖
spellingShingle U-Lin Hsu
許毓霖
Design of A Dual Mode Turbo/Convolutional Codec IP
author_sort U-Lin Hsu
title Design of A Dual Mode Turbo/Convolutional Codec IP
title_short Design of A Dual Mode Turbo/Convolutional Codec IP
title_full Design of A Dual Mode Turbo/Convolutional Codec IP
title_fullStr Design of A Dual Mode Turbo/Convolutional Codec IP
title_full_unstemmed Design of A Dual Mode Turbo/Convolutional Codec IP
title_sort design of a dual mode turbo/convolutional codec ip
publishDate 2003
url http://ndltd.ncl.edu.tw/handle/85719571319605059493
work_keys_str_mv AT ulinhsu designofadualmodeturboconvolutionalcodecip
AT xǔyùlín designofadualmodeturboconvolutionalcodecip
AT ulinhsu wōlúnmǎhuíxuánmǎshuāngmóshìbiānjiěmǎqìxìtǒngshèjìyǔshíxiàn
AT xǔyùlín wōlúnmǎhuíxuánmǎshuāngmóshìbiānjiěmǎqìxìtǒngshèjìyǔshíxiàn
_version_ 1718314379854741504