| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === This Paper present a design process and result of a dual mode turbo/ convolutional codec IP. It is obvious that the IP we designed have two major function. One is the encoding and decoding of the turbo code and the other is the encoding and decoding of the convolutional code.
As the increasing opportunities of the data transfer of the modern digital or mobile communication, the reliability of the data transfer has become more and more important. Therefore, the FEC have played an very important role nowadays. The motivation of this paper is to design an IP which could provide the ability of error control. The turbo code is one of the most popular of the error correcting code at present due to its correct ability of the burst errors. Besides, the convolutional and turbo code are adapted in the 3G mobile communication standard.This is why we intend to design a dual mode IP with the convolutional and turbo codec.
In this paper we introduce not only the conception and theorem but also the implementation of the IP. In the design process, we achieve software simulation of both two codec with C++ and then we implement it by Verilog. After the coding process with the verilog, we take use of the Xilinx foundation 4.1 to help us simulate the hardware we have designed.
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