| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === In this thesis, the implementation of single-phase power factor corrector has been effectively achieved with the aid of field programmable gate array (FPGA). By using the distributed arithmetic method, the number of configurable logic cells inside the FPGA can be reduced, facilitating the reduction of development cost. Besides, for the issue of output voltage sampling, a zero-point voltage sampling approach has been adopted in this thesis. With this strategy, the output voltage side can generate a equivalently virtual notch filter in order to replace the low-pass filter while the voltage can be thus better maintained at the predetermined value along with a fast response even under a drastic load variation. This proposed method has been validated through the software simulations and hardware implementation. Test results solidify the feasibility of the proposed method in both power factor improvement and voltage stabilization.
|
|---|
