Process Optimization and Electrical Characterization of High-K Gate Dielectric for ULSI Applications
博士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === The characteristics of high-K dielectrics for ULSI applications have been investigated. Additionally, optimization of technology processes has been developed to promote the characteristics of MOS devices with the high-K materials, including (a) nitrided oxide,...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2003
|
Online Access: | http://ndltd.ncl.edu.tw/handle/25997558701556284832 |
id |
ndltd-TW-091NCKU5442065 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-091NCKU54420652016-06-22T04:14:02Z http://ndltd.ncl.edu.tw/handle/25997558701556284832 Process Optimization and Electrical Characterization of High-K Gate Dielectric for ULSI Applications 應用於極大型積體電路的高介電閘極絕緣層電特性及製程最佳化的研究 Chih-Wei Yang 楊智偉 博士 國立成功大學 電機工程學系碩博士班 91 The characteristics of high-K dielectrics for ULSI applications have been investigated. Additionally, optimization of technology processes has been developed to promote the characteristics of MOS devices with the high-K materials, including (a) nitrided oxide, (b) hafnium dioxide (HfO2), (c) hafnium silicate (HfSiO), and (d) Hf-doped and NH3-nitrided thin films. Firstly, the characteristics and scalability of the ultrathin nitrided oxide formed by rapid thermal nitridation in NH3 ambient are investigated. Through NH3 thermal nitridation, it retains the initial base oxide thickness and concurrently introduces nitrogen concentration highly as 10%, exhibiting excellent downscaling ability. However, while the equivalent oxide thickness (EOT) of the nitrided oxide is below 15Å, the gate leakage current reaches 1A/cm2, which is too large for low-power and low-leakage devices applications, thus motivating us into the era of high-K dielectrics. Secondly, we comprehensively investigate the physical and electrical characteristics of hafnium dioxide (HfO2) formed by atomic layer chemical vapor deposition (ALCVD). The experimental results indicate that the dielectric constant of HfO2 is about 23, exhibiting dramatic reduction of gate leakage current in the magnitude of 6 to 8 orders. Additionally, process compatibility with polysilicon gate electrode is discussed and integration of HfO2 into conventionally CMOS process flow is succeeded. After process optimization of H2 and O2 post deposition annealing (PDA), polysilicon gate MOSFETs with HfO2 (EOT=23Å) exhibit degraded electron mobility (20% degradation) and almost intact hole mobility. Furthermore, factors leading to high threshold voltages in both N-type and P-type MOSFETs are investigated and a model based on interface traps at polysilicon/HfO2 interface is proposed. Thirdly, the characteristics of hafnium silicate (HfSiO) dielectric formed by metal organic chemical vapor deposition (MOCVD) are investigated. Although the addition of silicon in HfSiO film can raise the crystallization temperature, the electrical thickness of HfSiO is increased in response since the system k-value is decreased. With NH3 thermal nitridation prior to deposition of HfSiO can effectively tune the flatband voltage close to that of conventional oxide and significantly improve the leakage properties over SiO2 (3 orders reduction). Furthermore, the excellent interface quality has been evidenced by the result of immunity against soft breakdown with NH3 nitridation. The MOSFETs with HfSiO (EOT=22Å) exhibit significantly reduced electron mobility (~50% degradation) and slightly degraded hole mobility. Finally, in the viewpoint of reduced electron mobility and high threshold voltage described above, we propose a novel Hf-doped and NH3-nitrided high-K gate dielectric. First, we grow a high quality SiO2 by thermal oxidation of silicon substrate and then doped hafnium by ALCVD using HfCl4. Next, high temperature NH3 nitridation to remove Cl residues and concurrently introduce nitrogen to form HfSiON film. Followed by high temperature N2O annealing to stabilize the film. The HfSiON gate dielectric demonstrates excellent device performances such as only 10% degradation of electron mobility and almost 45 times of magnitude reduction in gate leakage compared to conventional SiO2 counterpart at the same equivalent oxide thickness (EOT). Additionally, negligible flatband voltage shift is achieved with this technique. Excellent performances in electrical stressing are also demonstrated by the dielectric. Yean-Kuen Fang Mong-Song Liang Shih-Chang Chen 方炎坤 梁孟松 陳世昌 2003 學位論文 ; thesis 135 en_US |
collection |
NDLTD |
language |
en_US |
format |
Others
|
sources |
NDLTD |
description |
博士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === The characteristics of high-K dielectrics for ULSI applications have been investigated. Additionally, optimization of technology processes has been developed to promote the characteristics of MOS devices with the high-K materials, including (a) nitrided oxide, (b) hafnium dioxide (HfO2), (c) hafnium silicate (HfSiO), and (d) Hf-doped and NH3-nitrided thin films.
Firstly, the characteristics and scalability of the ultrathin nitrided oxide formed by rapid thermal nitridation in NH3 ambient are investigated. Through NH3 thermal nitridation, it retains the initial base oxide thickness and concurrently introduces nitrogen concentration highly as 10%, exhibiting excellent downscaling ability. However, while the equivalent oxide thickness (EOT) of the nitrided oxide is below 15Å, the gate leakage current reaches 1A/cm2, which is too large for low-power and low-leakage devices applications, thus motivating us into the era of high-K dielectrics.
Secondly, we comprehensively investigate the physical and electrical characteristics of hafnium dioxide (HfO2) formed by atomic layer chemical vapor deposition (ALCVD). The experimental results indicate that the dielectric constant of HfO2 is about 23, exhibiting dramatic reduction of gate leakage current in the magnitude of 6 to 8 orders. Additionally, process compatibility with polysilicon gate electrode is discussed and integration of HfO2 into conventionally CMOS process flow is succeeded. After process optimization of H2 and O2 post deposition annealing (PDA), polysilicon gate MOSFETs with HfO2 (EOT=23Å) exhibit degraded electron mobility (20% degradation) and almost intact hole mobility. Furthermore, factors leading to high threshold voltages in both N-type and P-type MOSFETs are investigated and a model based on interface traps at polysilicon/HfO2 interface is proposed.
Thirdly, the characteristics of hafnium silicate (HfSiO) dielectric formed by metal organic chemical vapor deposition (MOCVD) are investigated. Although the addition of silicon in HfSiO film can raise the crystallization temperature, the electrical thickness of HfSiO is increased in response since the system k-value is decreased. With NH3 thermal nitridation prior to deposition of HfSiO can effectively tune the flatband voltage close to that of conventional oxide and significantly improve the leakage properties over SiO2 (3 orders reduction). Furthermore, the excellent interface quality has been evidenced by the result of immunity against soft breakdown with NH3 nitridation. The MOSFETs with HfSiO (EOT=22Å) exhibit significantly reduced electron mobility (~50% degradation) and slightly degraded hole mobility.
Finally, in the viewpoint of reduced electron mobility and high threshold voltage described above, we propose a novel Hf-doped and NH3-nitrided high-K gate dielectric. First, we grow a high quality SiO2 by thermal oxidation of silicon substrate and then doped hafnium by ALCVD using HfCl4. Next, high temperature NH3 nitridation to remove Cl residues and concurrently introduce nitrogen to form HfSiON film. Followed by high temperature N2O annealing to stabilize the film. The HfSiON gate dielectric demonstrates excellent device performances such as only 10% degradation of electron mobility and almost 45 times of magnitude reduction in gate leakage compared to conventional SiO2 counterpart at the same equivalent oxide thickness (EOT). Additionally, negligible flatband voltage shift is achieved with this technique. Excellent performances in electrical stressing are also demonstrated by the dielectric.
|
author2 |
Yean-Kuen Fang |
author_facet |
Yean-Kuen Fang Chih-Wei Yang 楊智偉 |
author |
Chih-Wei Yang 楊智偉 |
spellingShingle |
Chih-Wei Yang 楊智偉 Process Optimization and Electrical Characterization of High-K Gate Dielectric for ULSI Applications |
author_sort |
Chih-Wei Yang |
title |
Process Optimization and Electrical Characterization of High-K Gate Dielectric for ULSI Applications |
title_short |
Process Optimization and Electrical Characterization of High-K Gate Dielectric for ULSI Applications |
title_full |
Process Optimization and Electrical Characterization of High-K Gate Dielectric for ULSI Applications |
title_fullStr |
Process Optimization and Electrical Characterization of High-K Gate Dielectric for ULSI Applications |
title_full_unstemmed |
Process Optimization and Electrical Characterization of High-K Gate Dielectric for ULSI Applications |
title_sort |
process optimization and electrical characterization of high-k gate dielectric for ulsi applications |
publishDate |
2003 |
url |
http://ndltd.ncl.edu.tw/handle/25997558701556284832 |
work_keys_str_mv |
AT chihweiyang processoptimizationandelectricalcharacterizationofhighkgatedielectricforulsiapplications AT yángzhìwěi processoptimizationandelectricalcharacterizationofhighkgatedielectricforulsiapplications AT chihweiyang yīngyòngyújídàxíngjītǐdiànlùdegāojièdiànzhájíjuéyuáncéngdiàntèxìngjízhìchéngzuìjiāhuàdeyánjiū AT yángzhìwěi yīngyòngyújídàxíngjītǐdiànlùdegāojièdiànzhájíjuéyuáncéngdiàntèxìngjízhìchéngzuìjiāhuàdeyánjiū |
_version_ |
1718314107999879168 |