The Studies of High Performance Passive Devices with CMOS Compatible Technology for High Voltage and RF System Applications

• Main Authors: Chung-Hui CHen, 陳重輝
• Other Authors: Yean-Kuen Fang
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/08719542937822059275

博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 91 === The characteristics of passive devices with submicron CMOS compatible technology for high voltage and RF system applications have been investigated. Additionally, some advanced technologies have been developed to promote the characteristics of the developed passive devices. For high voltage polysilicon resistor, we use, (A) the nitrogen implantation to form a thin SiN layer on the top of the polysilicon resistor to prevent the hydrogen intrusion caused by the final passivation PECVD SiN from affecting the linearity of resistivity; (B) the thin oxide layer underneath the resistor to absorb the lateral arsenic dopant that was implanted to form the ohmic contact between the tungsten contact and the polysilicon. Because of the arsenic dopant segregate in the grain boundaries will deteriorate the voltage coefficient ratio of resistance (VCR) and the temperature coefficient ratio (TCR). (C) The optimization of DC current stress trimming for the high voltage polysilicon resistor under high current stress. With these technologies, the TCR, VCR, matching and the linearity of the resistivity of the high voltage polysilicon resistor are improved significantly. Next, for radio-frequency on-chip suspended spiral inductor, the oxide between the silicon substrate and the aluminum wire is removed by the CMOS process compatible post-processing wet-etch to reduce the substrate coupling loss and raise the quality factor as well as the self-resonance frequency. On the design of the suspended inductors we use the finite-element method simulation to analyze the mechanical stability. Furthermore, the diode-stacked NMOS device with only 250fF parasitic capacitance has been developed to protect the thin gate oxide of the 0.18um CMOS for high voltage and high frequency input-output circuits during the electro-static-discharge (ESD). Finally, we also propose a new scheme of copper interconnection with air-gap.