Hardware Implementation of Elliptic Curve Cryptosystem

• Main Authors: Ke-Yu Liu, 劉可玉
• Other Authors: Teh-Lu Liao
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/32495500531893434339

碩士 === 國立成功大學 === 工程科學系碩博士班 === 91 === Because the internet and mobile communication are getting popular [3], the transmission of the private data on the public channel is more frequent, for examples E-commerce, E-bank, and etc. Hence the security of private information transmission becomes more and more important. In general, encryption is an efficient method to protect the data from intruder’s attack. The public-key cryptosystem (PKC) and the secrete-key cryptosystem (SKC) are two major systems in data cryptosystem [1]. Since SKC has some unsolved drawbacks, we adopt PKC here. The security of public-key cryptosystems is based on the difficulty and complexity of mathematical problems. Now, there are three well-known types of cryptosystems: integer factorization systems (RSA), Elliptic curve discrete logarithm systems (elliptic curve cryptosystems) and discrete logarithm systems (ElGamal) [2]. In order to have higher security, a longer length of key size is needed. The increment of key size not only decreases the performance but also increases the cost of hardware. In 1985, Miller and Koblitz proposed the elliptic curve theory for the implementation of public-key cryptosystem. Hence the elliptic curve theory can be used to realize the ElGamal public-key cryptosystem. Its security is based on the Elliptic Curve Discrete Logarithm Problem (ECDLP). The advantage of ECC is that its key sizes are smaller than those of existing public-key cryptosystem (RSA, DSA) with equivalent levels of security so that it can be implemented in the devices that have memory and power constrains, like smart card or mobile phone. ECC is not a patent of any corporation so it can be applied freely. In this thesis, we adopt the ElGamal protocol and developed the hardware implementation of the elliptic curve cryptosystem by using Verilog HDL. The architecture of system consists of three parts: Shift Register, ECC Unit and Divider. Shift Register is design by using the concept of Linear Feedback Shift Register so that we can use an 8-bits register to generate a 255-bits pseudo sequence. The multiplier used in this thesis was suggested by C.K Koc and B. Sunar. Because its structures are very regular, it is easy to expend the bit size of multiplier. And it needs fewer gate counts and gate time delays than other multipliers, so it can be implemented in hardware. We adopt the Pipelined Divider attached in Xilinx Language Templates and improve its functions for using in the proposed ECC system. In addition, we adopt the concept of the Projective Space in order to convert the coordinates so that we can solve the operation complexity of inverse. Furthermore, we use a Low-Complexity Bit-Parallel Canonical and Normal Basis Multiplier. We use the concept of resource-sharing to avoid waste of hardware. Therefore, the hardware design of ECC is regular, secure and high performance.