| Summary: | 碩士 === 義守大學 === 資訊工程學系 === 91 === Recently, the NIST announced Rijndael algorithm to be a new encryption standard to replace the unreliable DES system [10]. In this thesis, we try to increase the robustness and safe of AES (Advanced Encryption Standard). This is another way increasing the security without security the simplicity of AES. In [8], a method to design for diversity is proposed. This method can increase the robustness with effectiveness on encryption system.
To implement the hardware for a diversity system, the analyses of the variation on AES take place first. Then, a core generator is built to load the code into lookup tables (LUTs). This method can use different parameters and tables and incorporates an FPGA (Field Programmable Gate Array) based to enhance the functionality on security. This design has an architecture using a S-Box generators with extra inputs This system is much more secure even losing its key. We have finished the new AES system the tested on a PCI based test-bench.
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