Low-Power Differential Circuits with Charge-Redistribution and Reduced-Swing Schemes

• Main Authors: Yang, Chou, 周暘
• Other Authors: Hong-Yi Huang
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/28032063355903478051

碩士 === 輔仁大學 === 電子工程學系 === 91 === The charge-redistribution low-swing differential logic (CLDL) circuits, including the charge-redistribution low-swing differential, the reduced precharge swing CLDL, RPS CLDL and the reduced output swing CLDL, RPS CLDL. The CLDL circuit utilizes the charge-redistribution and reduced-swing scheme to reduce the power dissipation and the current sense amplifier to quickly amplify the difference between the two output nodes of the logic network. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock (TSPC), thereby achieving high-speed operation. Then use the TSMC standard 0.35um CMOS process to comparison the performance. The CLDLs at least can reach 1GHz, more than 25% to other differential logic circuits; and faster 56% than N-C2MOS and PHIMOS. We can find that the advantage of RPS CLDL and ROS CLDL in power-delay product when operating in the maximum frequency. In power consumption, CLDLs reduce more 31% smaller than N-C2MOS and PHIMOS in power-delay product, and the RPS CLDL and ROS CLDL even more 42%. The CLDLs also have a advantage with which can correct operating when the supply voltage down to 1.1~1.3V.