| Summary: | 碩士 === 逢甲大學 === 資訊工程所 === 91 === Abstract
This thesis presents the design and implementation of PCI controller (PCI-32MT) with 32-bits data width. The PCI-32MT consists of two sub-modules: (1) PCI_TARGER unit─ It accepts read/write transactions originating from PCI bus and switches them into AHB (advanced high performance bus) of advanced microprocessor bus architecture (AMBA). (2) AMBA_TARGET unit─ It accepts read/write transactions originating from AHB and switches them into PCI bus. There are FIFOs inside the PCI-32MT communicating two independent clock domains and improving the whole performance. PCI-32MT makes users spend less effort to integrate application specific designs and the PCI controller together. It had been simulated with MODELSIM simulation tool to verified its’ functionality. The prototyping is established by synthesizing with ALTERA QUARTUS synthesizer. Finally, the programmable file is downloaded into FPGA. We use one application example to demonstrate that the core’s correctness. The device driver is developed by WINDRIVER. Finally, simple graphical user interface that provides user controllability is developed in C++.
Keyword: PCI, AMBA, AHB, BUS, FIFO
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