| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 91 === The aim of this thesis is to design a low voltage charge pump phase locked loop ( CP-PLL ) for clock generator applications. The core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter, divider and crystal oscillator.
PLLs contain several circuits: First, the frame of nc-PFD is used to eliminate the dead-zone in the PLL. With an added modified circuit, the proposed PFD overcomes the disadvantage of nc-PFD. The outputs UP and down ( DN ) will never rise at the same time. Second, the VCO is based on a four stages ring oscillator where each stage is a voltage controlled differential delay cell with dual delay paths. The VCO prevents the jitter noise from the power line and substrate. Finally, we use the second order loop filter to decrease the influence of voltage step and filter out the higher frequency noise from phase frequency detector and charge pump. A Pierce crystal oscillator is implemented in the system, which providing a stable 16.62MHz signal to the PLL.
The chip has been implemented in the TSMC 0.35μm 1P4M CMOS technology and the layout area of the crystal oscillator is 370x430μm2. The crystal oscillator can be used at resonating frequencies of 16~25MHz. The layout area of the PLL is 400 x 650μm2. For 3V power supply, the input frequency is 16.62MHz that provides by crystal oscillator, and the output frequencies are 16.62MHz, 33.24MHz, and 66.48MHz. The jitter of the output was approximate 270ps at 16.62MHz. The proposed PLL can be used in clock generator and frequency synthesizer applications.
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