Non-zero Skew Clock Tree Design Automation System
碩士 === 中原大學 === 電子工程研究所 === 91 === As the process technology enters the deep sub-micron design era, the design of clock tree has become one of the primary factors limiting circuit performance, process-variation-tolerant and a major source of power dissipation. Although the clock skew between registe...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/sb53nf |