Non-zero Skew Clock Tree Design Automation System

• Main Authors: Yu-Hui Lin, 林鈺惠
• Other Authors: Shin-Hsu Huang
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/sb53nf

碩士 === 中原大學 === 電子工程研究所 === 91 === As the process technology enters the deep sub-micron design era, the design of clock tree has become one of the primary factors limiting circuit performance, process-variation-tolerant and a major source of power dissipation. Although the clock skew between registers has been previously recognized as a manageable resource, the objective of commercially available layout tools is zero skew or a fixed skew bound. In this thesis, we will present a practical non-zero skew clock tree design methodology, which can be incorporated into ECO stage of the existing ASIC design flow. Our design methodology can not only increase the circuit performance and the circuit reliability, but also decrease the power dissipation and area. Given an initial clock tree, which is synthesized by commercially available layout tool, a gate-sizing algorithm is proposed to optimize the clock tree under the constraint that the double and zero clocking hazards do not occur. The proposed algorithm has been implemented in a C program. Benchmark data consistently shows that our design methodology achieves very good results in terms of the performance enhancement, reliability enhancement, power reduction and area decrease.