| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 91 === As the semiconductor proceeding technology enters deep submicron era, the timing-driven placement approach for very large circuits becomes more important. This paper presents a timing-driven quadrisection partition-based placement for VLSI standard cell circuit. The placement algorithm is implemented based on the principle that delay on critical paths must be carefully controlled during the placement procedure. In the partitioning and placement process, the length of a net is estimated by using star model. The net delay is estimated by applying the Elmore delay model. It allows to calculate an individual delay between the source pin and each sink pin of a net. Besides, we use a modified pre-locking mechanism to control the critical paths.
We use Design Compiler of Synopsys to find the critical paths information. The experimental result shows that, using the Elmore delay can obtain a better timing result than net-cut method. However, if we include the pre-locking mechanism then the critical path delay will be shorter. Experimental results and figure are shown in chapter 5.
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