A Parameterized and Dynamic Pipelined Low-Power Transform IP Core Design and Its Performance Analysis Platform

A Parameterized and Dynamic Pipelined Low-Power Transform IP Core Design and Its Performance Analysis Platform

碩士 === 國立中正大學 === 資訊工程研究所 === 91 ===

Bibliographic Details
Main Authors:	Li-Ting Yeh, 葉力廷
Other Authors:	Prof. Jiun-In Guo
Format:	Others
Language:	zh-TW
Published:	2003
Online Access:	http://ndltd.ncl.edu.tw/handle/13299032388972450627

Similar Items

An IP Generator for Multifunctional Discrete Transforms using Parameterized Modules
by: Chung-Han Lee, et al.
Published: (2004)

The Design and Verification of an IP Core for Pipeline AES Based on AXI4 Interface
by: Yu-Sung Chang, et al.
Published: (2019)

Parameterized IP Generator for High-Speed Viterbi Decoding
by: Ming-Chang Lee, et al.
Published: (2006)

Low-Power Design and Implement of the Multi-MPEG Motion Compensation IP Core
by: Lin-Chieh Huang, et al.
Published: (2004)

Dynamic Timing Simulation for Network-on-Chip with Parameterized Router Pipeline Architectures and Arbitration Policies
by: Yu, Chao-Kai, et al.
Published: (2014)

Parameterization dynamics visual design platform for missile launching system
by: Haigen Yang, et al.
Published: (2019-02-01)

A low power 10bit 200Ms/s Pipelined ADC
by: Chen, Yi-Ting, et al.
Published: (2017)

Single Camera 3D Visual Localization based on SIFT and Inverse Depth Parameterization Techniques
by: Ko -Ting Yeh, et al.
Published: (2007)

Parameterized DSP Core for Communication System
by: YA-LAN TSAO, et al.
Published: (2005)

Simultaneous Core Partitions: Parameterizations and Sums
by: Wang, Victor Y.
Published: (2016)

A Low-Cost On-Chip SOC Debug Platform with On-Line Monitor Capability for System Bus and IP Cores
by: Shao-Yuan Chen, et al.
Published: (2008)

Design and Implementation of the High-performance Low Power Multi-MPEG Bitstream Processing IP Core
by: Ying-Ming Tsai, et al.
Published: (2004)

From Escherichia coli mutant 13C labeling data to a core kinetic model: A kinetic model parameterization pipeline.
by: Charles J Foster, et al.
Published: (2019-09-01)

Low Power Mixed-Signal SoC Integration and Verification Challenges with Third Party IP Cores
by: Ruchi Shankar, et al.
Published: (2019-11-01)

A High Performance Low Power Multi-MPEG Variable Length Decoder IP Core Design
by: Tai-Lun Chang, et al.
Published: (2004)

Dynamic parameterization of IPSEC
by: Agar, Christopher D.
Published: (2012)

A Parameterized On-Chip-Bus-Compliant FDWT/IDWT Accelerator IP Generator
by: Chih-Chun Chang, et al.
Published: (2004)

A Low-Cost On-Chip SoC Debug Platform with Hardware Breakpoint Insertion and Single Step Capabilities for IP Cores
by: Si-Yuan Liang, et al.
Published: (2008)

Implementing the IPSec VPN in a dynamic IP network
by: Yeh,Hui-Huang, et al.
Published: (2005)

Low power techniques for pipelined ADC
by: Jia-Ming He, et al.

Application of Parameterization in Chinese Traditional Wooden Structural Components ─ as exemplified by the Main Hall of Taipei Rinzai (Linji) Buddhism Temple (Hu Guo Chan Si)
by: Li-Ning Yeh, et al.
Published: (2016)

A Low-power Convolutional Decoder with Error Detection Ability
by: Wei-ting Yeh, et al.
Published: (2010)

A High-Performance/Low-Power Mixed Static/Dynamic Circuit Synthesizer
by: Zhong-Ting Ye, et al.
Published: (2005)

A decision tree algorithm for investigation of model biases related to dynamical cores and physical parameterizations
by: M. Soner Yorgun, et al.
Published: (2016-12-01)

A Reconfigurable and Parameterized Hardware Accelerating IP for MPEG-4 Audio Coding and Reverberation
by: Guo-An Jian, et al.
Published: (2005)

The Non-sequential IP Lookup Mechanism Based on Pipeline
by: Hsaio-wen Huang, et al.
Published: (2010)

A Pipelined IP Forwarding Engine with Fast Update
by: Yen-cheng Liu, et al.
Published: (2008)

Development of Ferromagnetic Metallic Glasses into Low Loss Power Transformer Cores
by: Floyd, Michael Cameron Dawley
Published: (2018)

Partial core power transformer
by: Zhong, Ming
Published: (2013)

Dynamically reconfigurable parameterized components
by: Sridhar, Nigamanth
Published: (2004)

Dynamic Low-Delay Scheduling for Wireless Body Area Networks
by: Yeh,Wei-Ting, et al.
Published: (2018)

Design and Analysis of Memory Interface Architecture for Many-Core Platforms
by: Yeh, Kuo Kai, et al.
Published: (2015)

A Parameterized Silicon IP Design and Realization for the 1-D Variable Length Discrete Fourier Transform Using Block-based Distributed Arithmetic
by: Chien Chang Lin, et al.
Published: (2003)

An ultra-low-power processor pipeline-structure
by: Deng Tianchuan, et al.
Published: (2019-06-01)

Low-Power Pipelined Analog-to-Digital Converter
by: Chai, Yun, et al.
Published: (2012)

Low Power Optimization for a Pipelined VLIWArchitecture
by: Liang-Chie Wong, et al.
Published: (2005)

Bipartition and Synthesis in Low Power Pipelined Circuits
by: Huang, Xian-June, et al.
Published: (1997)

Bipartition and Synthesis in Low Power Pipelined Circuits
by: Huang, Xian-Jun, et al.
Published: (1997)

Fish the ChIPs: a pipeline for automated genomic annotation of ChIP-Seq data
by: Minucci Saverio, et al.
Published: (2011-10-01)

Power Management for a Many-core Platform
by: Ullström, Sebastian
Published: (2012)

Cannot write session to /tmp/vufind_sessions/sess_jp6mvm1d829iqhfbk8jnf8m0k5