Efficient Hardware/Software Co-design with System Software Co-simulation via Native Translation

• Main Authors: Ming-Lun Liu, 劉明倫
• Other Authors: Tien-Fu Chen
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/43299696572914011209

碩士 === 國立中正大學 === 資訊工程研究所 === 91 === In the past years, System-on-Chip (SOC) becomes an industry in great demand. As the chip designs reach larger gate counts and time-to-market windows shrink, the cost of simulation and vari‾cation in the process of hardware/software co-design rises outstandingly. Slowdown is one of the most important factors of simulations, since the practicability of the simulation depends on the length of the simulation time. In this thesis, we introduce a native translator which is embedded in the instruction-set simulator, translating the translatable basic blocks of in the target program been found out automatically. The experimental results will show our proposed mechanism can reduce the lowdown of the instruction-set simulator remarkably. We also implemented a simple scheduler that demonstrates the system software co-simulation with native translation is a practical process which could be considered a way to achieve the hardware/software co-design.