Routability Analysis of VLSI Circuits
碩士 === 元智大學 === 資訊工程學系 === 90 === With the advancement of semiconductor process, the routing problem is becoming more complex than ever before. If there is an unroutable net on a chip, a router will spend a lot of time on rerouting. In order to effectively achieve 100% routing, routabilit...
Main Authors: | , |
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Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2002
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Online Access: | http://ndltd.ncl.edu.tw/handle/91527189269750681034 |
Summary: | 碩士 === 元智大學 === 資訊工程學系 === 90 === With the advancement of semiconductor process, the routing problem is becoming more complex than ever before. If there is an unroutable net on a chip, a router will spend a lot of time on rerouting. In order to effectively achieve 100% routing, routability analysis should be performed for a design after placement and before routing to obtain the information about routing resources and routing demands. In the thesis, we first analyze the wires routed by a commercial router to understand the routing behavior. Then, a post placement routability analyzer based on the wiring distribution of routed nets will be developed. This analyzer consists of two major parts. A Routing Resource and Routing Demand Quantifier computes the routing demands for a given design. It builds a congestion map for showing congestion regions. A Routing Resource Tuner properly increases or decreases tracks in a region to either remove congestion or minimize chip area. The congestion map generated by our approach will be compared to the actual routing of a chip to see the effectiveness of our approach. The experimental results show that our routability analysis can actually predict most of the congestion regions. The Routing Resource Tuner can predict the required channel capacity within about 1.5 tracks difference from the exact number tracks needed for a complete routing.
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